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Data Orchestration in Deep Learning Accelerators

Data Orchestration in Deep Learning Accelerators

Tjek vores konkurrenters priser
This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore''s Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.
Tjek vores konkurrenters priser
Normalpris
kr 573
Fragt: 39 kr
6 - 8 hverdage
20 kr
Pakkegebyr
God 4 anmeldelser på
Tjek vores konkurrenters priser
This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore''s Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.
Produktdetaljer
Sprog: Engelsk
Sider: 146
ISBN-13: 9783031006395
Indbinding: Paperback
Udgave:
ISBN-10: 3031006399
Udg. Dato: 18 aug 2020
Længde: 0mm
Bredde: 191mm
Højde: 235mm
Forlag: Springer International Publishing AG
Oplagsdato: 18 aug 2020
Forfatter(e) Tushar Krishna, Angshuman Parashar, Hyoukjun Kwon, Michael Pellauer, Ananda Samajdar


Kategori Elektronik: kredse og komponenter


ISBN-13 9783031006395


Sprog Engelsk


Indbinding Paperback


Sider 146


Udgave


Længde 0mm


Bredde 191mm


Højde 235mm


Udg. Dato 18 aug 2020


Oplagsdato 18 aug 2020


Forlag Springer International Publishing AG

Kategori sammenhænge